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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
Rev. 03 -- 16 July 2009 Product data sheet
1. General description
The PCA9541A is a 2-to-1 I2C-bus master selector designed for high reliability dual master I2C-bus applications where system operation is required, even when one master fails or the controller card is removed for maintenance. The two masters (for example, primary and back-up) are located on separate I2C-buses that connect to the same downstream I2C-bus slave devices. I2C-bus commands are sent by either I2C-bus master and are used to select one master at a time. Either master at any time can gain control of the slave devices if the other master is disabled or removed from the system. The failed master is isolated from the system and will not affect communication between the on-line master and the slave devices on the downstream I2C-bus. Two versions are offered for different architectures. PCA9541A/01 with channel 0 selected at start-up, and PCA9541A/03 with no channel selected after start-up. The interrupt outputs are used to provide an indication of which master has control of the bus. One interrupt input (INT_IN) collects downstream information and propagates it to the 2 upstream I2C-buses (INT0 and INT1) if enabled. INT0 and INT1 are also used to let the previous bus master know that it is not in control of the bus anymore and to indicate the completion of the bus recovery/initialization sequence. Those interrupts can be disabled and will not generate an interrupt if the masking option is set. A bus recovery/initialization if enabled sends nine clock pulses, a not acknowledge, and a STOP condition in order to set the downstream I2C-bus devices to an initialized state before actually switching the channel to the selected master. An interrupt is sent to the upstream channel when the recovery/initialization procedure is completed. An internal bus sensor senses the downstream I2C-bus traffic and generates an interrupt if a channel switch occurs during a non-idle bus condition. This function is enabled when the PCA9541A recovery/initialization is not used. The interrupt signal informs the master that an external I2C-bus recovery/initialization needs to be performed. It can be disabled and an interrupt will not be generated. The pass gates of the switches are constructed such that the VDD pin can be used to limit the maximum high voltage, which will be passed by the PCA9541A. This allows the use of different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V devices can communicate with 5 V devices without any additional protection. The PCA9541A does not isolate the capacitive loading on either side of the device, so the designer must take into account all trace and device capacitances on both sides of the device, and pull-up resistors must be used on all channels. External pull-up resistors pull the bus to the desired voltage level for each channel. All I/O pins are 6.0 V tolerant.
NXP Semiconductors
PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
An active LOW reset input allows the PCA9541A to be initialized. Pulling the RESET pin LOW resets the I2C-bus state machine and configures the device to its default state as does the internal Power-On Reset (POR) function.
2. Features
I I I I I I I I I I I I I I I I I I I I I I I 2-to-1 bidirectional master selector I2C-bus interface logic; compatible with SMBus standards PCA9541A/01 powers up with Channel 0 selected PCA9541A/03 powers up with no channel selected and either master can take control of the bus Active LOW interrupt input 2 active LOW interrupt outputs Active LOW reset input 4 address pins allowing up to 16 devices on the I2C-bus Channel selection via I2C-bus Bus initialization/recovery function Bus traffic sensor Low Ron switches Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses No glitch on power-up Supports hot insertion Software identical for both masters Low standby current Operating power supply voltage range of 2.3 V to 5.5 V 6.0 V tolerant inputs 0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO16, TSSOP16, HVQFN16
3. Applications
I I I I High reliability systems with dual masters Gatekeeper multiplexer on long single bus Bus initialization/recovery for slave devices without hardware reset Allows masters without arbitration logic to share resources
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
4. Ordering information
Table 1. Ordering information Tamb = -40 C to +85 C Type number PCA9541AD/01 PCA9541ABS/01 PCA9541AD/03 PCA9541ABS/03 Package Name SO16 HVQFN16 SO16 HVQFN16 PCA9541APW/01 TSSOP16 Description plastic small outline package; 16 leads; body width 3.9 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm Version SOT109-1 SOT403-1
plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; SOT629-1 body 4 x 4 x 0.85 mm plastic small outline package; 16 leads; body width 3.9 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT109-1 SOT403-1
PCA9541APW/03 TSSOP16
plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; SOT629-1 body 4 x 4 x 0.85 mm
5. Marking
Table 2. Marking codes Topside mark PCA9541AD/1 9541A/1 41A1 PCA9541AD/3 9541A/3 41A3 Type number PCA9541AD/01 PCA9541APW/01 PCA9541ABS/01 PCA9541AD/03 PCA9541APW/03 PCA9541ABS/03
PCA9541A_3
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
6. Block diagram
PCA9541A
SCL_MST0 SDA_MST0
INPUT FILTER
STOP DETECTION
BUS SENSOR
A3 A2 A1 A0 RESET VDD POWER-ON RESET
I2C-BUS CONTROL AND REGISTER BANK
SLAVE CHANNEL SWITCH CONTROL LOGIC
SCL_SLAVE SDA_SLAVE
SCL_MST1 SDA_MST1
INPUT FILTER
STOP DETECTION
BUS RECOVERY/ INITIALIZATION
OSCILLATOR
INT0 INT1 INTERRUPT LOGIC INT_IN
002aae656
VSS
Fig 1.
Block diagram of PCA9541A
PCA9541A_3
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Product data sheet
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
7. Pinning information
7.1 Pinning
PCA9541AD/01 PCA9541AD/03
INT0 SDA_MST0 SCL_MST0 RESET SCL_MST1 SDA_MST1 INT1 VSS 1 2 3 4 5 6 7 8
002aae657
16 VDD 15 INT_IN 14 SDA_SLAVE 13 SCL_SLAVE 12 A3 11 A2 10 A1 9 A0 INT0 SDA_MST0 SCL_MST0 RESET SCL_MST1 SDA_MST1 INT1 VSS 1 2 3 4 5 6 7 8
002aae658
16 VDD 15 INT_IN 14 SDA_SLAVE 13 SCL_SLAVE 12 A3 11 A2 10 A1 9 A0
PCA9541APW/01 PCA9541APW/03
Fig 2.
Pin configuration for SO16
16 SDA_MST0
Fig 3.
Pin configuration for TSSOP16
terminal 1 index area
SCL_MST0 RESET SCL_MST1 SDA_MST1
1 2 3 4 5 6 7 8
13 INT_IN 12 SDA_SLAVE 11 SCL_SLAVE 10 A3 9 A2 A1
15 INT0 VSS
PCA9541ABS/01 PCA9541ABS/03
INT1
A0
14 VDD
002aae659
Transparent top view
Fig 4.
Pin configuration for HVQFN16
PCA9541A_3
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Product data sheet
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
7.2 Pin description
Table 3. Symbol Pin description Pin SO16, TSSOP16 INT0 SDA_MST0 SCL_MST0 RESET SCL_MST1 SDA_MST1 INT1 VSS A0 A1 A2 A3 SCL_SLAVE SDA_SLAVE INT_IN VDD
[1]
Description HVQFN16 15 16 1 2 3 4 5 6[1] 7 8 9 10 11 12 13 14 active LOW interrupt output 0 (external pull-up required) serial data master 0 (external pull-up required) serial clock master 0 (external pull-up required) active LOW reset input (external pull-up required) serial clock master 1 (external pull-up required) serial data master 1 (external pull-up required) active LOW interrupt output 1 (external pull-up required) supply ground address input 0 (externally held to VSS or VDD) address input 1 (externally held to VSS or VDD) address input 2 (externally held to VSS or VDD) address input 3 (externally held to VSS or VDD) serial clock slave (external pull-up required) serial data slave (external pull-up required) active LOW interrupt input (external pull-up required) supply voltage
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
HVQFN16 package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the printed-circuit board in the thermal pad region.
PCA9541A_3
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
8. Functional description
Refer to Figure 1 "Block diagram of PCA9541A".
8.1 Device address
Following a START condition, the upstream master that wants to control the I2C-bus or make a status check must send the address of the slave it is accessing. The slave address of the PCA9541A is shown in Figure 5. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable pins and they must be pulled HIGH or LOW.
1
1 fixed
1
A3
A2
A1
A0 R/W
hardware selectable
002aab390
Fig 5.
Slave address
The last bit of the slave address defines the operation to be performed. When set to logic 1 a read is selected, while logic 0 selects a write operation. Remark: Reserved I2C-bus addresses must be used with caution since they can interfere with:
* `reserved for future use' I2C-bus addresses (1111 1XX) * slave devices that use the 10-bit addressing scheme (1111 0XX) 8.2 Command Code
Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9541A, which will be stored in the Command Code register.
0
0
0
AI
0
0
B1
B0
auto-increment
register number
002aab391
Fig 6.
Command Code
The 2 LSBs are used as a pointer to determine which register will be accessed. If the auto-increment flag is set (AI = 1), the two least significant bits of the Command Code are automatically incremented after a byte has been read or written. This allows the user to program the registers sequentially or to read them sequentially.
* During a read operation, the contents of these bits will roll over to 00b after the last
allowed register is accessed (10b).
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
* During a write operation, the PCA9541A will acknowledge bytes sent to the IE and
CONTROL registers, but will not acknowledge a byte sent to the Interrupt Status Register since it is a read-only register. The 2 LSBs of the Command Code do not roll over to 00b but stay at 10b. Only the 2 least significant bits are affected by the AI flag. Unused bits must be programmed with zeros. Any command code (write operation) different from `000AI 0000', `000AI 0001', and `000AI 0010' will not be acknowledged. At power-up, this register defaults to all zeros.
Table 4. B1 0 0 1 1 0 1 0 1 Command Code register B0 Register name IE CONTROL ISTAT not allowed Type R/W R/W R only Register function interrupt enable control switch interrupt status
Each system master controls its own set of registers, however they can also read specific bits from the other system master.
PCA9541A
IE CONTROL ISTAT REG#00 REG#01 REG#10 IE 0 CONTROL 0 ISTAT 0 IE 1 CONTROL 1 ISTAT 1 REG#00 REG#01 REG#10 IE CONTROL ISTAT
MASTER 0 SCL_MST0 SDA_MST0
002aae660
MASTER 1 SCL_MST1 SDA_MST1
Fig 7.
Internal register map
8.3 Interrupt Enable and Control registers description
When a master seeks control of the bus by connecting its I2C-bus channel to the PCA9541A downstream channel, it has to write to the CONTROL register (Reg#01). Bits MYBUS and BUSON allow the master to take control of the bus. The MYBUS and the NMYBUS bits determine which master has control of the bus. Table 9 explains which master gets control of the bus and how. There is no arbitration. Any master can take control of the bus when it wants regardless of whether the other master is using it or not. The BUSON and the NBUSON bits determine whether the upstream bus is connected or disconnected to/from the downstream bus. Table 10 explains when the upstream bus is connected or disconnected. Internally, the state machine does the following:
* If the combination of the BUSON and the NBUSON bits causes the upstream to be
disconnected from the downstream bus, then that is done. So in this case, the values of the MYBUS and the NMYBUS do not matter.
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Product data sheet
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
* If a master was connected to the downstream bus prior to the disconnect, then an
interrupt is sent on the respective interrupt output in an attempt to let that master know that it is no longer connected to the downstream bus. This is indicated by setting the BUSLOST bit in the Interrupt Status Register.
* If the combination of the BUSON and the NBUSON bits causes a master to be
connected to the downstream bus and if there is no change in the BUSON bits since when the disconnect took effect, then the master requesting the bus is connected to the downstream bus. If it requests a bus initialization sequence, then it is performed.
* If there is no change in the combination of the BUSON and the NBUSON bits and a
new master wants the bus, then the downstream bus is disconnected from the old master that was using it and the new master gets control of it. Again, the bus initialization if requested is done. The appropriate interrupt signals are generated. After a master has sent the bus control request: 1. The previous master is disconnected from the I2C-bus. An interrupt to the previous master is sent through its INT line to let it know that it lost control of the bus. BUSLOST bit in the Interrupt Status Register is set. This interrupt can be masked by setting the BUSLOSTMSK bit to logic 1. 2. A built-in bus initialization/recovery function can take temporary control of the downstream channel to initialize the bus before making the actual switch to the new bus master. This function is activated by setting the BUSINIT to logic 1 by the master during the same write sequence as the one programming MYBUS and BUSON bits. When activated and whether the bus was previously idle or not: a. 9 clock pulses are sent on the SCL_SLAVE. b. SDA_SLAVE line is released (HIGH) when the clock pulses are sent to SCL_SLAVE. This is equivalent to sending 8 data bits and a not acknowledge. c. Finally a STOP condition is sent to the downstream slave channel. This sequence will complete any read transaction which was previously in process and the downstream slave configured as a slave-transmitter should release the SDA line because the PCA9541A did not acknowledge the last byte. 3. When the initialization has been requested and completed, the PCA9541A sends an interrupt to the new master through its INT line and connects the new master to the downstream channel. BUSINIT bit in the Interrupt Status Register is set. The switch operation occurs after the master asking the bus control has sent a STOP command. This interrupt can be masked by setting the BUSINITMSK bit to logic 1. 4. When the bus initialization/recovery function has not been requested (BUSINIT = 0), the PCA9541A connects the new master to the slave downstream channel. The switch operation occurs after the master asking the bus control has sent a STOP command. PCA9541A sends an interrupt to the new master through its INT line if the built-in bus sensor function detects a non-idle condition in the downstream slave channel at the switching time. BUSOK bit in the Interrupt Status Register is set. This means that a STOP condition has not been detected in the previous bus communication and that an external bus recovery/initialization must be performed. If an idle condition has been detected at the switching time, no interrupt will be sent. This interrupt can be masked by setting the BUSOKMSK bit to logic 1. Interrupt status can be read. See Section 8.4 "Interrupt Status registers" for more information.
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
The MYTEST and the NMYTEST bits cause the interrupt pins of the respective masters to be activated for a `functional interrupt test'. Remark: The regular way to proceed is that a master asks to take the control of the bus by programming MYBUS and BUSON bits based on NMUYBUS and NBUSON values. Nevertheless, the same master can also decide to give up the control of the bus and give it to the other master. This is also done by programming the MYBUS and BUSON bits based on NMYBUS and NBUSON values. Remark: Any writes either to the Interrupt Enable Register or the Control Register cause the respective register to be updated on the 9th clock cycle, that is, on the rising edge of the acknowledge clock cycle. Remark: The actual switch from one channel to another or the switching off of both the channels happens on a STOP command that is sent by the master requesting the switch.
8.3.1 Register 0: Interrupt Enable (IE) register (B1:B0 = 00b)
This register allows a master to read and/or write (if needed) Mask options for its own channel. The Interrupt Enable register described below is identical for both the masters. Nevertheless, there are physically 2 internal Interrupt Enable registers, one for each upstream channel. When Master 0 reads/writes in this register, the internal Interrupt Enable Register 0 will be accessed. When Master 1 reads/writes in this register, the internal Interrupt Enable Register 1 will be accessed.
Table 5. 7 0 Register 0 - Interrupt Enable (IE) register (B1:B0 = 00b) bit allocation 6 0 5 0 4 0 3 BUSLOSTMSK 2 BUSOKMSK 1 BUSINITMSK 0 INTINMSK
Table 6. Register 0 - Interrupt Enable (IE) register bit description Legend: * default value Bit 7:4 3 Symbol BUSLOSTMSK Access Value[1] Description R only R/W 0* 0* 1 2 BUSOKMSK R/W 0* not used An interrupt on INT will be generated after the other master has been disconnected. An interrupt on INT will not be generated after the other master has been disconnected. After connection is requested and Bus Initialization not requested (BUSINIT = 0), an interrupt on INT will be generated when a non-idle situation has been detected on the downstream slave channel by the bus sensor at the switching moment. Remark: Channel switching is done automatically after the STOP command. 1 After connection is requested and Bus Initialization not requested (BUSINIT = 0), an interrupt on INT will not be generated when a non-idle situation has been detected on the downstream slave channel by the bus sensor at the switching moment (masked). Remark: Channel switching is done automatically after the STOP command.
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
Table 6. Register 0 - Interrupt Enable (IE) register bit description ...continued Legend: * default value Bit 1 Symbol BUSINITMSK Access Value[1] Description R/W 0* After connection is requested and Bus Initialization requested (BUSINIT = 1), an interrupt on INT will be generated when the bus initialization is done. Remark: Channel switching is done after bus initialization completed. 1 After connection is requested and Bus Initialization requested (BUSINIT = 1), an interrupt on INT will not be generated when the bus initialization is done (masked). Remark: Channel switching is done after bus initialization completed. 0 INTINMSK R/W 0* 1
[1]
Interrupt on INT_IN will generate an interrupt on INT. Interrupt on INT_IN will not generate an interrupt on INT (masked)
Default values are the same for PCA9541A/01, PCA9541A/03.
8.3.2 Register 1: Control Register (B1:B0 = 01b)
The Control Register described below is identical for both the masters. Nevertheless, there are physically 2 internal Control Registers, one for each upstream channel. When master 0 reads/writes in this register, the internal Control Register 0 will be accessed. When master 1 reads/writes in this register, the internal Control Register 1 will be accessed.
Table 7. 7 NTESTON Register 1 - Control Register (B1:B0 = 01b) bit allocation 6 TESTON 5 0 4 BUSINIT 3 NBUSON 2 BUSON 1 NMYBUS 0 MYBUS
Table 8. Register 1 - Control Register (B1:B0 = 01b) bit description Legend: * default value Bit 7 Symbol NTESTON Access Value[1] R/W 0* 1 6 5 4 3 TESTON BUSINIT NBUSON R/W R only R/W R only 0* 1 0* 0* 1 see Table 11 see Table 11 see Table 11 see Table 11 Description A logic level HIGH to the INT line of the other channel is sent (interrupt cleared). A logic level LOW to the INT line of the other channel is sent (interrupt generated). A logic level HIGH to the INT line is sent (interrupt cleared). A logic level LOW to the INT line is sent (interrupt generated). not used Bus initialization is not requested. Bus initialization is requested. NBUSON bit along with BUSON bit decides whether any upstream channel is connected to the downstream channel or not. See Table 10, Table 11, and Table 12. BUSON bit along with the NBUSON bit decides whether any upstream channel is connected to the downstream channel or not. See Table 10, Table 11, and Table 12. NMYBUS bit along with MYBUS bit decides which upstream channel is connected to the downstream channel. See Table 9, Table 11, and Table 12. MYBUS bit along with the NMYBUS bit decides which upstream channel is connected to the downstream channel. See Table 9, Table 11, and Table 12.
2
BUSON
R/W
1 0
NMYBUS MYBUS
R only R/W
[1]
Default values are the same for PCA9541A/01, PCA9541A/03.
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
Table 9. MYBUS and NMYBUS truth table As a master reads its Control Register NMYBUS[1] MYBUS[1] 0 1 0 1
[1]
Slave channel The master reading this combination has control of the bus. The master reading this combination does not have control of the bus. The master reading this combination does not have control of the bus. The master reading this combination has control of the bus.
0 0 1 1
MYBUS and NMYBUS is an exclusive-OR type function where: Equal values (00b or 11b) means that the master reading its Control Register has control of the bus. Different values (01b or 10b) means that the master reading its Control Register does not have control of the bus.
Table 10. 0 1 0 1
[1]
BUSON and NBUSON truth table BUSON[1] 0 0 1 1 Slave channel off on on off
NBUSON[1]
BUSON and NBUSON is an exclusive-OR type function where: Equal values (00b or 11b) means that the connection between the upstream and the downstream channels is off. Different values (01b or 10b) means that the connection between the upstream and the downstream channels is on.
Switch to the new channel is done when the master initiating the switch request sends a STOP command to the PCA9541A. If either master wants to change the connection of the downstream channel, it needs to write to its Control Register (Reg#01), and then send a STOP command because an update of the connection to the downstream according to the values in the two internal Control Registers happens only on a STOP command. Writing to one control register followed by a STOP condition on the other master's channel will not cause an update to the downstream connection. When both masters request a switch to their own channel at the same time, the master who last wrote to its Control Register before the PCA9541A receives a STOP command wins the switching sequence. There is no arbitration performed. The Auto Increment feature (AI = 1) allows to program the PCA9541A in 4 bytes: Start 111A3A2A1A0 + 0 00010000 Data Reg#00 Data Reg#01 Stop
PCA9541 Address + Write Select Reg#00 with AI = 1 Interrupt Enable Register data Control Register data
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
Table 11.
Default Control Register values Master Bit 7 0 0 0 0 Bit 6 0 0 0 0 Bit 5 not used 0 0 0 0 Bit 4 BUSINIT 0 0 0 0 Bit 3 NBUSON 0 1 0 0 Bit 2 BUSON 1 0 0 0 Bit 1 NMYBUS 0 1 0 1 Bit 0 MYBUS 0 0 0 0 NTESTON TESTON
Type version
PCA9541A/01 MST_0 MST_1 PCA9541A/03 MST_0 MST_1
Table 12 describes which command needs to be written to the Control Register when a master device wants to take control of the I2C-bus. Byte written to the Control Register is a function of the current I2C-bus control status performed after an initial reading of the Control Register. Current status of the I2C-bus is determined by the bits MYBUS, NMYBUS, BUSON and NBUSON is one of the following:
* * * *
The master reading its Control Register does not have control and the I2C-bus is off. The master reading its Control Register does not have control and the I2C-bus is on. The master reading its Control Register has control and the I2C-bus is off. The master reading its Control Register has control and the I2C-bus is on.
`I2C-bus off' means that upstream and downstream channels are not connected together. `I2C-bus on' means that upstream and downstream channels are connected together. Remark: Only the 4 LSBs of the Control Register are described in Table 12 since only those bits control the I2C-bus control. The logic value for the 4 MSBs is specific to the application and are not discussed in the table. The read sequence is performed by the master as: S - 111xxxx0 - 000x0001 - Sr - 111xxxx1 - DataRead - P The write sequence is performed by the master as: S - 111xxxx0 - 000x0001 - DataWritten - P
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Product data sheet Rev. 03 -- 16 July 2009 [1] [2] [3]
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Table 12. Byte read[1] Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F
Bus control sequence Write Control Register performed by the master NMYBUS MYBUS Byte written[1][2] Hex bus off bus off bus off bus off bus on bus on bus on bus on bus on bus on bus on bus on bus off bus off bus off bus off has control no control no control has control has control no control no control has control has control no control no control has control has control no control no control has control 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 4 4 5 5 4 5 0 1 0 0 1 1 bus on bus on, take control bus on, take control bus on no change take control take control no change no change take control take control no change bus on bus on, take control bus on, take control bus on x x x x x x x x x x x x 1 1 1 1 1 1 x x x x x x 0 0 1 1 0 1 Action performed to take mastership NBUSON[3] BUSON NMYBUS[3] MYBUS Status NBUSON BUSON
Read Control Register performed by the master
no write required
no write required no write required 0 0 0 0 0 0 x x x x x x 0 1 0 0 1 1
2-to-1 I2C-bus master selector with interrupt logic and reset
no write required
Only the 4 LSBs are shown. x0x0 in binary = 0, 2, 8 or A in hexadecimal x0x1 in binary = 1, 3, 9 or B in hexadecimal x1x0 in binary = 4, 6, C or E in hexadecimal x1x1 in binary = 5, 7, D or F in hexadecimal x can be either `0' or `1' since those bits are read-only bits.
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
8.4 Interrupt Status registers
The PCA9541A provides 4 different types of interrupt:
* To indicate to the former I2C-bus master that it is not in control of the bus anymore * To indicate to the new I2C-bus master that:
- The bus recovery/initialization has been performed and that the downstream channel connection has been done (built-in bus recovery/initialization active). - A `bus not well initialized' condition has been detected by the PCA9541A when the switch has been done (built-in bus recovery/initialization not active). This information can be used by the new master to initiate its own bus recovery/initialization sequence.
* Indicate to both I2C-bus upstream masters that a downstream interrupt has been
generated through the INT_IN pin.
* Functionality wiring test.
8.4.1 Bus control lost interrupt
When an upstream master takes control of the I2C-bus while the other channel was using the downstream channel, an interrupt is generated to the master losing control of the bus (INT line goes LOW to let the master know that it lost the control of the bus) immediately after disconnection from the downstream channel. By setting the BUSLOSTMSK bit to `1', the interrupt is masked and the upstream master that lost the I2C-bus control does not receive an interrupt (INT line does not go LOW).
8.4.2 Recovery/initialization interrupt
Before switching to a new upstream channel, an automatic bus recovery/initialization can be performed by the PCA9541A. This function is requested by setting the BUSINIT bit to `1'. When the downstream bus has been initialized, an interrupt to the new master is generated (INT line goes LOW). By setting the BUSINITMSK bit to `1', the interrupt is masked and the new master does not receive an interrupt (INT line does not go LOW). When the automatic bus recovery/initialization is not requested, if the built-in bus sensor function (sensing permanently the downstream I2C-bus traffic) detects a non-idle condition (previous bus channel connected to the downstream slave channel, was between a START and STOP condition), then an interrupt to the new master is sent (INT line goes LOW). This interrupt tells the new master that an external bus recovery/initialization must be performed. By setting the BUSOKMSK bit to `1', the interrupt is masked and the new master does not receive an interrupt (INT line does not go LOW). Remark: In this particular situation, after the switch to the new master is performed, a read of the Interrupt Status Register is not possible if the switch happened in the middle of a read sequence because the new master does not have control of the SDA line.
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
8.4.3 Downstream interrupt
An interrupt can also be generated by a downstream device by asserting the INT_IN pin LOW. When INT_IN is asserted LOW and if both INTINMSK bits are not set to `1' by either master, INT0 and INT1 both go LOW. By setting the INTINMSK bit to `1' by a master and/or the INTINMSK bit to `1' by the other master, the interrupt(s) is (are) masked and the corresponding masked channel(s) does (do) not receive an interrupt (INT0 and/or INT1 line does (do) not go LOW).
8.4.4 Functional test interrupt
A master can send an interrupt to itself to test its own INT wire or send an interrupt to the other master to test its INT line. This is done by:
* setting the TESTON bit to `1' to test its own INT line * setting the NTESTON bit to `1' to test the other master INT line
Setting the TESTON and/or NTESTON bits to `0' by a master will clear the interrupt(s). Remark: Interrupt outputs have an open-drain structure. Interrupt input does not have any internal pull-up resistor and must not be left floating (that is, pulled HIGH to VDD through resistor) in order to avoid any undesired interrupt conditions.
8.4.5 Register 2: Interrupt Status Register (B1:B0 = 10b)
The Interrupt Status Register for both the masters is identical and is described below. Nevertheless, there are physically 2 internal Interrupt Registers, one for each upstream channel. When Master 0 reads this register, the internal Interrupt Register 0 will be accessed. When Master 1 reads this register, the internal Interrupt Register 1 will be accessed.
Table 13. 7 NMYTEST Register 2 - Interrupt Status register (B1:B0 = 10b) bit allocation 6 MYTEST 5 0 4 0 3 BUSLOST 2 BUSOK 1 BUSINIT 0 INTIN
Table 14. Register 2 - Interrupt Status (ISTAT) register bit description Legend: * default value Bit 7 Symbol NMYTEST[2] Access Value[1] Description R only 0* 1 6 5 4 3 MYTEST[2] BUSLOST[4] R only R only R only R only 0* 1 0* 0* 0* 1 no interrupt generated due to NTESTON bit from the other master (NTESTON = 0 from the other master)[3] interrupt generated due to TESTON bit from the other master (NTESTON = 1 from the other master)[3] no interrupt generated by TESTON bit (TESTON = 0)[3] interrupt generated by TESTON bit (TESTON = 1)[3] not used not used no interrupt generated to the previous master when switching to the new one is initiated interrupt generated to the previous master when switching to the new one is initiated
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
Table 14. Register 2 - Interrupt Status (ISTAT) register bit description ...continued Legend: * default value Bit 2 Symbol BUSOK[4] Access Value[1] Description R only 0* 1 1 BUSINIT[4] R only 0* 1 0 INTIN[2] R only 0* 1
[1] [2]
no interrupt generated by bus sensor function interrupt generated by bus sensor function (masked when bus recovery/initialization requested) - Bus was not idle when the switch occurred no interrupt generated by the bus recovery/initialization function interrupt generated by the bus recovery/initialization function; recovery/initialization done no interrupt on interrupt input (INT_IN)[5] interrupt on interrupt input (INT_IN)[5]
Default values are the same for PCA9541A/01 and PCA9541A/03. Reading the Interrupt Status Register does not clear the MYTEST, NMYTEST or the INTIN bits. They are cleared if: INT_IN lines goes HIGH for INTIN bit TESTON bit is cleared for MYTEST bit NTESTON bit is cleared for NMYTEST bit Interrupt on a master is cleared after TESTON bit is cleared by the same master or NTESTON bit is cleared by the other master. BUSINIT, BUSOK and BUSLOST bits in the Interrupt Status Register get cleared after a read of the same register is done. Precisely, the register gets cleared on the second clock pulse during the read operation. If the interrupt condition remains on INT_IN after the read sequence, another interrupt will be generated (if the interrupt has not been masked).
[3] [4] [5]
8.5 Power-on reset
When power is applied to VDD, an internal power-on reset holds the PCA9541A in a reset condition until VDD has reached VPOR. At this point, the reset condition is released and the internal registers are initialized to their default states, with:
* PCA9541A/01: default Channel 0 (no STOP detect)
After power-up and/or insertion of the device in the main I2C-bus, the upstream Channel 0 and the downstream slave channel are connected together.
* PCA9541A/03: default `no channel' (no STOP detect)
After power-up and/or insertion of the device in the main I2C-bus, no channel will be connected to the downstream channel. The device is ready to receive a START condition and its address by a master. If either register writes to its Control Register, then the connection between the upstream and the downstream channels is determined by the values on the Control Registers. Thereafter, VDD must be lowered below 0.2 V to reset the device.
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
8.6 External reset
A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst)L. The PCA9541A registers and I2C-bus state machine will be held in their default states until the RESET input is once again HIGH. This input typically requires a pull-up resistor to VDD. Default states are:
* I2C-bus upstream Channel 0 connected to the I2C-bus downstream channel for the
PCA9541A/01
* no I2C-bus upstream channel connected to the I2C-bus downstream channel for the
PCA9541A/03.
8.7 Voltage translation
The pass gate transistors of the PCA9541A are constructed such that the VDD voltage can be used to limit the maximum voltage that will be passed from one I2C-bus to another.
5.0 Vo(sw) (V) 4.0
(1)
002aaa964
3.0
(2) (3)
2.0
1.0 2.0
2.5
3.0
3.5
4.0
4.5
5.5 5.0 VDD (V)
(1) maximum (2) typical (3) minimum
Fig 8.
Pass gate voltage as a function of supply voltage
Figure 8 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using the data specified in Section 12 "Static characteristics" of this data sheet). In order for the PCA9541A to act as a voltage translator, the Vo(sw) voltage should be equal to, or lower than the lowest bus voltage. For example, if the main buses were running at 5 V, and the downstream bus was 3.3 V, then Vo(sw) should be equal to or below 3.3 V to effectively clamp the downstream bus voltages. Looking at Figure 8, we see that Vo(sw)(max) will be at 3.3 V when the PCA9541A supply voltage is 3.5 V or lower so the PCA9541A supply voltage could be set to 3.3 V. Pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see Figure 17). More Information on voltage translation can be found in Application Note AN262: PCA954X family of I2C/SMBus multiplexers and switches.
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
9. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
9.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 9).
SDA
SCL data line stable; data valid change of data allowed
mba607
Fig 9.
Bit transfer
9.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 10).
SDA
SCL S START condition P STOP condition
mba608
Fig 10. Definition of START and STOP conditions
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
9.3 System configuration
A device generating a message is a `transmitter', a device receiving is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves' (see Figure 11).
SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER
SLAVE
002aaa966
Fig 11. System configuration
9.4 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition 1 2 8 clock pulse for acknowledgement
002aaa987
9
Fig 12. Acknowledgement on the I2C-bus
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
9.5 Bus transactions
data Interrupt Enable (IE) register A acknowledge from slave
slave address
command code register
data control register (CONTROL) AP acknowledge from slave STOP condition
002aab607
S 1 1 1 A3 A2 A1 A0 0 A 0 0 0 1 0 0 0 0 A START condition R/W acknowledge from slave auto increment acknowledge from slave
Fig 13. Write to the Interrupt Enable and Control registers using the Auto-Increment (AI) bit
Remark: If a third data byte is sent, it will not be acknowledged by the PCA9541A.
slave address
command code register access to register xx = 00, 01, or 10 x
slave address
S 1 1 1 A3 A2 A1 A0 0 A 0 0 0 1 0 0 START condition R/W acknowledge from slave
(1)
x A Sr 1 1 1 A3 A2 A1 A0 1 A re-START condition R/W acknowledge from slave
(3)
auto increment
acknowledge from slave
(2)
A acknowledge from master
A acknowledge from master
AP no acknowledge from master STOP condition
002aab608
(1) xx = 00: Interrupt Enable register xx = 01: Control register xx = 10: INT register (2) xx = 00: Control register xx = 01: INT register xx = 10: Interrupt Enable register (3) xx = 00: INT register xx = 01: Interrupt Enable register xx = 10: Control register
Fig 14. Read the 3 registers using the Auto-Increment (AI) bit
Remark: If a fourth data byte is read, the first register will be accessed.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Product data sheet Rev. 03 -- 16 July 2009
(c) NXP B.V. 2009. All rights reserved. PCA9541A_3
NXP Semiconductors
SDA_MST0(1) slave address
command code register
data Control register
After the STOP condition MASTER 1 is disconnected from the downstream channel.
S 1 1 1 A3 A2 A1 A0 0 A 0 0 0 AI 0 0 0 1 A 0 0 0 1 0 1 0 0 A P START condition R/W acknowledge from slave SCL_MST0 auto increment acknowledge from slave
BUSINIT BUSON MYBUS acknowledge from slave
STOP condition
INT1
2-to-1 I2C-bus master selector with interrupt logic and reset
if the interrupt is not masked (BUSLOSTMSK = 0) SCL_SLAVE 123456789
SDA_SLAVE A INT0 STOP command if the interrupt is not masked (BUSINITMSK = 0) MASTER 1 has control of the bus PCA9541 has control of the bus MASTER 0 must wait for the 'bus free time' value (between STOP and START) defined in the I2C-bus specification before sending commands to the downstream devices.
002aab609
MASTER 0 has control of the bus
PCA9541A
22 of 41
(1) We assume that a read of the Control register was done by MASTER 0 before this sequence and that 000x 0101 was read (MASTER 1 controlling the bus).
Fig 15. Write to the Control register and switch from Channel 1 to Channel 0 (bus recovery/initialization requested)
NXP Semiconductors
PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
SDA_MST0(1) slave address
command code register
data Control register
After the STOP condition MASTER 1 is disconnected from the downstream channel, and MASTER 0 is connected to the downstream channel.
S 1 1 1 A3 A2 A1 A0 0 A 0 0 0 AI 0 0 0 1 A 0 0 0 0 0 1 0 0 A P START condition R/W acknowledge from slave SCL_MST0 auto increment acknowledge from slave STOP condition
BUSINIT BUSON MYBUS acknowledge from slave
INT1 if the interrupt is not masked (BUSLOSTMSK = 0) INT0 if MASTER 1 was not idle at the switching moment and the interrupt is not masked (BUSINITMSK = 0) MASTER 1 has control of the bus MASTER 0 must wait for the 'bus free time' value (between STOP and START) defined in the I2C-bus specification before sending commands to the downstream devices. MASTER 0 has control of the bus
002aab610
(1) We assume that a read of the Control register was done by MASTER 0 before this sequence and that 000x 0101 was read (MASTER 1 controlling the bus).
Fig 16. Write to the Control register and switch from Channel 1 to Channel 0 (bus recovery/initialization not requested)
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
10. Application design-in information
SLAVE CARD 3.3 V VDD MASTER 0 SCL0 SDA0 RESET0 INT0 VSS SDA_SLAVE SCL_SLAVE RESET 3.3 V VDD MASTER 1 SCL1 SDA1 RESET1 INT1 VSS A3 A2 A1 A0 VSS INT1 SCL_MST1 SDA_MST1 SDA SCL SLAVE 1 SDA SCL SLAVE 3 INT0 VDD SCL_MST0 SDA_MST0
PCA9541A
INT_IN
SLAVE 2 INT SDA SCL
002aae661
Fig 17. Typical application
10.1 Specific applications
The PCA9541A is a 2-to-1 I2C-bus master selector designed for dual master, high reliability I2C-bus applications, where continuous maintenance and control monitoring is required even if one master fails or its controller card is removed for maintenance. The PCA9541A can also be used in other applications, such as where masters share the same resource but cannot share the same bus, as a gatekeeper multiplexer in long single bus applications or as a bus initialization/recovery device.
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
10.2 High reliability systems
In a typical multipoint application, shown in Figure 18, the two masters (for example, primary and back-up) are located on separate I2C-buses that connect to multiple downstream I2C-bus slave cards/devices via a PCA9541A/01 for non-hot swap applications to provide high reliability of the I2C-bus.
PCA9541A
PCA9541A
PCA9541A
PCA9541A
PCA9541A
PCA9541A
PCA9541A
PCA9541A
MASTER 0
SCL1 SDA1
002aae662
Fig 18. High reliability backplane application
I2C-bus commands are sent via the primary or back-up master and either master can take command of the I2C-bus. Either master at any time can gain control of the slave devices if the other master is disabled or removed from the system. The failed master is isolated from the system and will not affect communication between the on-line master and the slave devices located on the cards. For even higher reliability in multipoint backplane applications, two dedicated masters can be used for every card as shown in Figure 19.
PCA9541A
MASTER 0
SCL1 SDA1
PCA9541A
MASTER 0
SCL1 SDA1
PCA9541A
MASTER 0
SCL1 SDA1
PCA9541A
MASTER 0
SCL1 SDA1
002aae663
Fig 19. Very high reliability backplane application
PCA9541A_3
Product data sheet
Rev. 03 -- 16 July 2009
MASTER 1
SCL0 SDA0
MASTER 1
SCL0 SDA0
MASTER 1
SCL0 SDA0
MASTER 1
SCL0 SDA0
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MASTER 1
SCL0 SDA0
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
10.3 Masters with shared resources
Some masters may not be multi-master capable or some masters may not work well together and continually lock up the bus. The PCA9541A can be used to separate the masters, as shown in Figure 20, but still allow shared access to slave devices, such as Field Replaceable Unit (FRU) EEPROMs or temperature sensors.
ASSEMBLY A
SDA/SCL SLAVE A2
MASTER A
PCA9541A
SLAVE A0 MAIN MASTER
SLAVE A1
ASSEMBLY B
SDA/SCL SLAVE B2
MASTER B
PCA9541A
SLAVE B0
SLAVE B1
002aae664
Fig 20. Masters with shared resources application
10.4 Gatekeeper multiplexer
The PCA9541A/03 can act as a gatekeeper multiplexer in applications where there are multiple I2C-bus devices with the same fixed address (for example, EEPROMs with address of `Z' as shown in Figure 21) connected in a multipoint arrangement to the same I2C-bus. Up to 16 hot swappable cards/devices can be multiplexed to the same bus master by using one PCA9541A/03 per card/device. Since each PCA9541A/03 has its own unique address (for example, `A', `B', `C', and so on), the EEPROMs can be connected to the master, one at a time, by connecting one PCA9541A/03 (Master 0 position) while keeping the rest of the cards/devices isolated (off position). The alternative, shown with dashed lines, is to use a PCA9548 1-to-8 channel switch on the master card and run 8 I2C-bus devices, one to each EEPROM card, to multiplex the master to each card. The number of card pins used is the same in either case, but there are 7 less pairs of SDA/SCL traces on the printed-circuit board if the PCA9541A/03 is used.
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
PCA9541A
PCA9541A
PCA9541A
PCA9541A
PCA9541A
PCA9541A
PCA9541A
A
B
C
D
E
F
G
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
Z
Z
Z
Z
Z
Z
Z
002aae665
Fig 21. Gatekeeper multiplexer application
10.5 Bus initialization/recovery to initialize slaves without hardware reset
If the I2C-bus is hung, I2C-bus devices without a hardware reset pin (for example, Slave 1 and Slave 2 in Figure 22) can be isolated from the master by the PCA9541A/03. The PCA9541A/03 disconnects the bus when it is reset via the hardware reset line, restoring the master's control of the rest of the bus (for example, Slave 0). The bus master can then command the PCA9541A/03 to send 9 clock pulses/STOP condition to reset the downstream I2C-bus devices before they are reconnected to the master or leave the downstream devices isolated.
SDA/SCL MASTER SLAVE 1
PCA9541A/03
SLAVE 0 RESET
SDA SCL SLAVE 2
slave I2C-bus
002aae666
Fig 22. Bus initialization/recovery application
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EEPROM Z
PCA9548
PCA9541A
H
MASTER 0
NXP Semiconductors
PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
11. Limiting values
Table 15. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS (ground = 0 V).[1] Symbol VDD VI II IO IDD ISS Ptot Tstg Tamb
[1]
Parameter supply voltage input voltage input current output current supply current ground supply current total power dissipation storage temperature ambient temperature
Conditions
Min -0.5 -0.5 -20 -25 -100 -100 -60
Max +7.0 +7.0 +20 +25 +100 +100 400 +150 +85
Unit V V mA mA mA mA mW C C
operating in free air
-40
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 125 C.
12. Static characteristics
Table 16. Static characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Supply VDD IDD supply voltage supply current Operating mode; no load; VI = VDD or VSS; fSCL = 100 kHz VDD = 3.6 V VDD = 5.5 V Istb standby current Standby mode; no load; VI = VDD or VSS; fSCL = 0 kHz VDD = 3.6 V VDD = 5.5 V VPOR VIL VIH IOL IL Ci power-on reset voltage LOW-level input voltage HIGH-level input voltage LOW-level output current VOL = 0.4 V VOL = 0.6 V leakage current input capacitance VI = VDD or VSS VI = VSS VDD = 2.3 V to 3.6 V VDD = 3.6 V to 5.5 V 4 4 5 6 pF pF no load; VI = VDD or VSS
[1]
Parameter
Conditions
Min 2.3
Typ -
Max 3.6
Unit V
-
152 349
200 600
A A
-0.5 0.7VDD 3 6 -1
30 40 1.5 -
80 100 2.1 +0.3VDD 6 +1
A A V V V mA mA A
Input SCL_MSTn; input/output SDA_MSTn (upstream and downstream channels)
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
Table 16. Static characteristics ...continued VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol VIL VIH ILI Ci Parameter LOW-level input voltage HIGH-level input voltage input leakage current input capacitance VI = VDD or VSS VI = VSS VDD = 2.3 V to 3.6 V VDD = 3.6 V to 5.5 V Pass gate Ron ON-state resistance VDD = 4.5 V to 5.5 V; VO = 0.4 V; IO = 15 mA VDD = 3.0 V to 3.6 V; VO = 0.4 V; IO = 15 mA VDD = 2.3 V to 2.7 V; VO = 0.4 V; IO = 10 mA Vo(sw) switch output voltage Vi(sw) = VDD = 5.0 V; Io(sw) = -100 A Vi(sw) = VDD = 4.5 V to 5.5 V; Io(sw) = -100 A Vi(sw) = VDD = 3.3 V; Io(sw) = -100 A Vi(sw) = VDD = 3.0 V to 3.6 V; Io(sw) = -100 A Vi(sw) = VDD = 2.5 V; Io(sw) = -100 A Vi(sw) = VDD = 2.3 V to 2.7 V; Io(sw) = -100 A IL IOL
[1]
Conditions
Min -0.5 0.7VDD -1 4 5 7 2.6 1.6 1.1 -1 3
Typ 2 2 12 14 17 3.6 2.2 1.5 -
Max +0.3VDD 6 +1 3 5 24 30 55 4.5 2.8 2.0 +1 -
Unit V V A pF pF V V V V V V A mA
Select inputs A0 to A3, INT_IN, RESET
leakage current
VI = VDD or VSS
INT0 and INT1 outputs LOW-level output current VOL = 0.4 V
VDD must be lowered to 0.2 V in order to reset part.
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PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
13. Dynamic characteristics
Table 17. Symbol Dynamic characteristics Parameter Conditions Standard-mode Fast-mode I2C-bus Unit I2C-bus Min tPD propagation delay (SDA_MSTn to SDA_SLAVE) or (SCL_MSTn to SCL_SLAVE)
[1]
Max 0.3
Min -
Max 0.3 ns
-
fSCL fSCL(init/rec) tBUF tHD;STA tLOW tHIGH tSU;STA tSU;STO tHD;DAT tSU;DAT tr tf Cb tSP tVD;DAT tVD;ACK INT
SCL clock frequency SCL clock frequency (bus initialization/bus recovery) bus free time between a STOP and START condition hold time (repeated) START condition LOW period of the SCL clock HIGH period of the SCL clock set-up time for a repeated START condition set-up time for STOP condition data hold time data set-up time rise time of both SDA and SCL signals fall time of both SDA and SCL signals capacitive load for each bus line pulse width of spikes that must be suppressed by the input filter data valid time data valid acknowledge time HIGH-to-LOW LOW-to-HIGH
[5] [5] [2]
0 50 4.7 4.0 4.7 4.0 4.7 4.0 0[3] 250 INT_IN input INT_IN input 1 0.5 10 SDA clear
[6][7]
100 150 3.45 1000 300 400 50 1 0.6 1 4 2 -
0 50 1.3 0.6 1.3 0.6 0.6 0.6 0[3] 100 20 + 0.1Cb[4] 20 + 0.1Cb 1 0.5 10 500 0
[4]
400 150 0.9 300 300 400 50 1 0.6 1 4 2 -
kHz kHz s s s s s s s ns ns ns pF ns s s s s s s s ns ns ns
tv(INT_IN-INTn) valid time from pin INT_IN to pin INTn signal td(INT_IN-INTn) delay time from pin INT_IN to pin INTn inactive tw(rej)L tw(rej)H RESET tw(rst)L trst tREC;STA
[1] [2] [3]
LOW-level rejection time HIGH-level rejection time LOW-level reset time reset time recovery time to START condition
500 0
Pass gate propagation delay is calculated from the 20 typical Ron and the 15 pF load capacitance. After this period, the first clock pulse is generated. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
(c) NXP B.V. 2009. All rights reserved.
PCA9541A_3
Product data sheet
Rev. 03 -- 16 July 2009
30 of 41
NXP Semiconductors
PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
[4] [5] [6] [7]
Cb = total capacitance of one bus line in pF. Measurements taken with 1 k pull-up resistor and 50 pF load. Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions. Upon reset, the full delay will be the sum of trst and the RC time constant of the SDA bus.
SDA tBUF tLOW SCL tr tf tHD;STA tSP
tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr
tSU;STA
tSU;STO P
002aaa986
Fig 23. Definition of timing on the I2C-bus
protocol
START condition (S) tSU;STA
bit 7 MSB (A7) tLOW tHIGH
bit 6 (A6)
bit 0 (R/W)
acknowledge (A)
STOP condition (P)
1/f
SCL
SCL tBUF tr tf
SDA
tHD;STA
tSU;DAT
tHD;DAT
tVD;DAT
tVD;ACK
tSU;STO
002aab175
Rise and fall times, refer to VIL and VIH.
Fig 24. I2C-bus timing diagram
PCA9541A_3
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Product data sheet
Rev. 03 -- 16 July 2009
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NXP Semiconductors
PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
START SCL
ACK or read cycle
SDA 30 % trst
RESET
50 % tREC;STA
50 % tw(rst)L
50 %
trst INTn 50 %
002aae735
Fig 25. Definition of RESET timing
14. Test information
6.0 V open VSS
VDD PULSE GENERATOR VI DUT
RT
VO
RL 500
CL 50 pF
002aab393
Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 26. Test circuitry for switching times
PCA9541A_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 16 July 2009
32 of 41
NXP Semiconductors
PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
15. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 pin 1 index Lp 1 e bp 8 wM L detail X A1 (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
0.010 0.057 0.069 0.004 0.049
0.019 0.0100 0.39 0.014 0.0075 0.38
0.244 0.041 0.228
0.028 0.004 0.012
8 o 0
o
ISSUE DATE 99-12-27 03-02-19
Fig 27. Package outline SOT109-1 (SO16)
PCA9541A_3 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 16 July 2009
33 of 41
NXP Semiconductors
PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c y HE vMA
Z
16
9
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
8
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18
Fig 28. Package outline SOT403-1 (TSSOP16)
PCA9541A_3 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 16 July 2009
34 of 41
NXP Semiconductors
PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm
SOT629-1
D
B
A
terminal 1 index area E
AA 1 c
detail X
e1
1/2 e
C b 8 vMCAB wMC y1 C y
e 5 L
4
9 e
Eh
1/2 e
e2
1 12
terminal 1 index area
16 Dh 0
13 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.38 0.23 c 0.2 D (1) 4.1 3.9 Dh 2.25 1.95 E (1) 4.1 3.9 Eh 2.25 1.95 e 0.65 e1 1.95 e2 1.95 L 0.75 0.50 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT629-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22
Fig 29. Package outline SOT629-1 (HVQFN16)
PCA9541A_3 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 16 July 2009
35 of 41
NXP Semiconductors
PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
PCA9541A_3 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 16 July 2009
36 of 41
NXP Semiconductors
PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
16.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 30) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 18 and 19
Table 18. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 19. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 30.
PCA9541A_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 16 July 2009
37 of 41
NXP Semiconductors
PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 30. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
17. Abbreviations
Table 20. Acronym AI CDM DUT EEPROM ESD FRU HBM I2C-bus IC MM POR RC SMBus Abbreviations Description Auto Increment Charged Device Model Device Under Test Electrically Erasable Programmable Read-Only Memory ElectroStatic Discharge Field Replaceable Unit Human Body Model Inter Integrated Circuit bus Integrated Circuit Machine Model Power-On Reset Resistor-Capacitor network System Management Bus
PCA9541A_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 16 July 2009
38 of 41
NXP Semiconductors
PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
18. Revision history
Table 21. Revision history Release date 20090716 Data sheet status Product data sheet 3rd Change notice paragraph. Supersedes PCA9541A_2 Document ID PCA9541A_3 Modifications:
* *
Section 1 "General description": deleted (old)
Section 12 "Static characteristics": merged Table 16 "Static characteristics" (VDD = 2.3 V to 3.6 V) and (old) Table 17 "Static characteristics" (VDD = 3.6 V to 5.5 V). Product data sheet Objective data sheet PCA9541A_1 -
PCA9541A_2 PCA9541A_1
20090604 20090528
PCA9541A_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 16 July 2009
39 of 41
NXP Semiconductors
PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
19. Legal information
19.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
19.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
20. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9541A_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 16 July 2009
40 of 41
NXP Semiconductors
PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
21. Contents
1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.3.1 8.3.2 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.5 8.6 8.7 9 9.1 9.2 9.3 9.4 9.5 10 10.1 10.2 10.3 10.4 10.5 11 12 13 14 15 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 7 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 7 Command Code . . . . . . . . . . . . . . . . . . . . . . . . 7 Interrupt Enable and Control registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Register 0: Interrupt Enable (IE) register (B1:B0 = 00b) . . . . . . . . . . . . . . . . . . . . . . . . . 10 Register 1: Control Register (B1:B0 = 01b) . . 11 Interrupt Status registers . . . . . . . . . . . . . . . . 15 Bus control lost interrupt . . . . . . . . . . . . . . . . . 15 Recovery/initialization interrupt. . . . . . . . . . . . 15 Downstream interrupt . . . . . . . . . . . . . . . . . . . 16 Functional test interrupt . . . . . . . . . . . . . . . . . 16 Register 2: Interrupt Status Register (B1:B0 = 10b) . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 17 External reset . . . . . . . . . . . . . . . . . . . . . . . . . 18 Voltage translation . . . . . . . . . . . . . . . . . . . . . 18 Characteristics of the I2C-bus. . . . . . . . . . . . . 19 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 START and STOP conditions . . . . . . . . . . . . . 19 System configuration . . . . . . . . . . . . . . . . . . . 20 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 20 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 21 Application design-in information . . . . . . . . . 24 Specific applications . . . . . . . . . . . . . . . . . . . . 24 High reliability systems . . . . . . . . . . . . . . . . . . 25 Masters with shared resources. . . . . . . . . . . . 26 Gatekeeper multiplexer . . . . . . . . . . . . . . . . . . 26 Bus initialization/recovery to initialize slaves without hardware reset . . . . . . . . . . . . 27 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 28 Static characteristics. . . . . . . . . . . . . . . . . . . . 28 Dynamic characteristics . . . . . . . . . . . . . . . . . 30 Test information . . . . . . . . . . . . . . . . . . . . . . . . 32 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 33 16 16.1 16.2 16.3 16.4 17 18 19 19.1 19.2 19.3 19.4 20 21 Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 36 36 36 37 38 39 40 40 40 40 40 40 41
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 16 July 2009 Document identifier: PCA9541A_3

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